The present invention relates in general to digital bus architectures and, more particularly, to a digital bus data retention scheme.
Most if not all computer systems use a digital bus architecture to transfer address and data signals between the central processing unit, memory and various peripherals. Typically, data is placed on the bus by a data driver. A latching circuit then latches the data at its output for use by the appropriate end device. It is important for the data to remain valid on the bus between the time the data driver charges the bus and the time the latching circuit reads the data.
A conventional digital bus may use a pre-charge transistor to initialize the bus to say logic one. The data driver then sets the proper logic level on the bus according to a data input signal. Such a scheme relies on bus capacitance to hold the data on the bus until the latch can read it. The data retention time is thus limited by the capacitive discharge time on the bus. Another known technique is to connect the input and output of a bus keeper buffer to the data bus. The buffer is typically two series inverters with a drive capacity much less than the data drivers. Thus, the data driver simply overpowers the buffer to change logic state on the bus. Unfortunately, conventional bus keeper buffers are sensitive to noise because of their small size and may change state inadvertently from noise due to adjacent bus switching.
Hence, a need exists for a data retention scheme to maintain valid data on the data bus indefinitely while remaining robust to noise.